1. Field of the Invention
The present invention relates to semiconductor devices having a vertical surrounding gate transistor (SGT) structure, methods for manufacturing the semiconductor devices, and data processing systems which include the semiconductor devices.
Priority is claimed on Japanese Patent Application No. 2007-251348, filed Sep. 27, 2007, the content of which is incorporated herein by reference.
2. Description of Related Art
Highly integrated and high performance semiconductor devices have been realized, for the most part, by the refinement of transistors. However, in recent years, it is becoming difficult to simply refine transistors. In the future, it will be difficult to realize highly integrated and high performance semiconductor devices by only the refinement of planar metal oxide semiconductor (MOS) transistors which has been performed so far. Therefore, transistors having a three-dimensional structure have been investigated as a measure of refining transistors.
For example, a three-dimensional transistor having a vertical SGT structure disclosed in Japanese Unexamined Patent Application, First Publication No. H05-136374 (hereinafter referred to as “Patent Document 1”) employs a silicon pillar extending along the direction orthogonal to the principal plane of a semiconductor substrate as a channel of a transistor. As shown in FIG. 1 of Patent Document 1, a semiconductor substrate 1 has a semiconductor pillar (the silicon pillar) which functions as the channel. A gate electrode 2 is provided around the pillar with a gate insulating film 5 interposed therebetween. A drain region 3 is provided on a side of a lower part of the pillar. A source region 4 is provided at an upper portion of the pillar. A source electrode 6 is connected to the source region 4 with an insulating film 70 interposed therebetween to form a metal insulation semiconductor (MIS) capacitor. There are also provided: a channel stopper 10 and a field insulating film 11 for device separation; and an insulating film 8 which insulates the source region 4 and the drain region 3 from the source electrode 6 and a drain electrode 9.
The present inventor has recognized the following matters.
When the gate length of a transistor is extremely small, the influence of the short channel effect increases and it becomes difficult to control the threshold voltage of the transistor. In addition, the S value increases, and a higher threshold voltage is required from the viewpoint of a reduction in current during the transistor is turned off. An increase in threshold voltage due to an increase in the S value makes it difficult to realize semiconductor devices which operate at a low voltage. If shallow diffused layers of a source and a drain of a transistor are formed in order to alleviate the short channel effect, current is reduced due to increases in resistance of the source and the drain. Moreover, with respect to cell transistors provided in dynamic random access memories (DRAMs), shallow diffused layers increase a junction leak current, thereby deteriorating the refresh characteristics of the DRAMs.
In accordance with a transistor having a three-dimensional structure, the area occupied by the transistor is small. Moreover, the area occupied by the transistor does not increase even if the channel length (the gate length) is increased. Therefore, it is possible to suppress the short channel effect without increasing the area occupied by the transistor. Furthermore, since it is possible to fully deplete the channel, a satisfactory S value and a large drain current can be obtained. In addition, since a gate electrode is formed so as to cover the entire perimeter of the channel having a pillar shape, it is possible to eliminate external factors other than those of a source and a drain and to effectively control the potential of the channel by means of a voltage applied to the gate electrode.
However, in order to fully deplete the channel of a three-dimensional transistor, it is necessary to reduce (thin) the diameter of a silicon pillar which forms the channel. Although depending on the density of impurities in the channel; a voltage applied to a gate; voltages respectively applied to a source and a drain; and the density of impurities in the source and the drain, as a guideline, the diameter of a silicon pillar which allows full depletion of the channel is double or less the height of the silicon pillar, which determines the distance between the source and the drain. If the diameter of the silicon pillar increases, the channel of the transistor is unable to be fully depleted, the S value is deteriorated drastically, the influences of the source and the drain become significant, and the influence of the short channel effect increases. In other words, the characteristics of the transistor approach those of planar transistors.
The drain current of transistors employing a silicon pillar is proportional to the diameter of the silicon pillar which forms the channel. The drain current can be increased by increasing the diameter of the silicon pillar. However, if the diameter of the silicon pillar is increased, the transistors are unable to be fully depleted, so that the characteristics of the transistors are deteriorated drastically. Thus, the drain current of fully depleted transistors employing a silicon pillar is limited. When a large drain current is required, the threshold voltage is increased instead of increasing the diameter of the silicon pillar so as to prevent the S value from being deteriorated. In addition, since the influence of the short channel effect becomes significant, it is necessary to, for example, change the profile of the diffused layers of the source and the drain. However, this leads to an increase in resistance of the diffused layers of the source and the drain, thereby reducing the drain current further.